Certain embodiments of the present invention relate to the synthesis of a clock signal. More specifically, certain embodiments relate to a method and apparatus for efficiently synthesizing a clock signal on a chip such that the synthesized clock signal has a 50% duty cycle. The synthesized clock signal is derived from a system clock signal that is at half the frequency of the synthesized clock signal and whose duty cycle is not required to be 50%.
Highly integrated System-on-Chip (SOC) implementations require clock synthesis and generation to be available on-chip. High speed and high-density memory designs require precise clocking elements to meet timing requirements. For example, one application is to double clock an embedded memory to make the embedded memory appear as a dual port. Double clocking may be accomplished, in part, by doubling the frequency of an existing system clock signal.
Many embedded on-chip clock synthesis implementations consume significant amounts of power and chip area and also are dependent on the duty cycle of a system clock signal from which the synthesized clock signal is being derived. It is often desirable for a synthesized clock signal to have a 50% duty cycle, being independent of the clock signal from which the synthesized clock signal is derived. It is also desirable to synthesize a clock signal in an efficient manner to minimize power consumed and chip area consumed by the clock synthesizing circuitry.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with embodiments of the present invention as set forth in the remainder of the present application with reference to the drawings.